This invention is related to frequency control circuits such as phase locked loops (PLLs), delay locked loops (DLLs), and clock recovery circuit (CRC) units.
Frequency control circuits are used in a wide range of applications. For instance, a PLL or DLL may be used to eliminate jitter or skew in a clock signal. A CRC unit locks the phase of a reference clock signal to an input data signal and provides a synchronized data output by sampling the input data signal and synchronizing the sample with the controlled reference clock. In a typical frequency control unit, the phase of an input oscillatory signal is compared to the phase of an output oscillatory signal, and the phase error between these signals is driven to zero using a process that controls the frequency of the output signal and features negative feedback. The term "control bandwidth" refers to the rate at which the process is updated with the most recent phase error information.
At relatively high control bandwidths, it becomes very difficult to ensure that the manufactured version of the frequency control unit can measure the phase error and reliably update the process as designed, particularly when using a low cost integrated circuit (IC) solution that would be more effective at lower frequencies. A limited solution to this problem is to use a parallel phase detector array in which each parallel element measures the phase error at different times and at a lower rate then the "combined" rate of the array as a whole. For instance, if each element of a five-element parallel phase detector is able to measure the phase error at 200 MHz but at a slightly different time, then the detector as a whole is effectively measuring the phase error at five times the rate of each element, or 1 GHz.
In practice, however, the theoretical approach outlined above has not been successful in fully taking advantage of the reduction in the speed of operation of each element of the parallel phase detector array. For instance, in frequency control circuits that use an array of parallel detector elements all of which control the same charge pump (gated current source), the so-called "up" and "down" pulses that are generated by each phase detector element must be active only when that particular element contains the most recent measurement of the phase error to properly control the charge pump. In CRC units, this has translated into the undesirable requirement that the up and down pulses be no wider than the length (from a time point of view) of a "bit cell" in the data signal received by the CRC unit. This means that at least some of the devices which form the integrated circuit CRC unit must operate at the same speed as the control bandwidth of the CRC unit. The disadvantage here is that once the limit of device operating speed has been reached in a frequency control circuit fabricated using a given IC manufacturing process, a different, "faster" manufacturing process must be used to increase the control bandwidth.